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readable-verilog-generator
Eriemon/verilog-generatorSkill
Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
Why this score
Popularity score: 69/100 from public GitHub signals only. It shows how widely used and maintained this is, not how well it works. Not included yet: the fake-star check. The security scan is shown separately and doesn't change the score. How we rank
Security
Scanned Oct 20, 2026 at commit 007372fb63fe, first 300 source files (it's a large repo), with Cisco's open-source skill-scanner.
What its code does:
- Reads environment variables, where API keys usually livescripts/python/installation/cli.py:269, scripts/python/remote/remote_validate_execution.py:730, scripts/python/validation/validate_verilog_skill.py:994 and 3 more
A scan lists patterns in the code. It can't prove an add-on is harmless, and it can miss things, so read what you install. How we scan
Alternatives
Nothing from another maker does quite the same job yet.